A limiting circuit is needed to restrict signal magnitude to a proper level when large changes of the input signal might have undesirable effects, i.e. saturation of circuit components, on an amplifier, an analog-to-digital converter (ADC), etc. which receives the signal. For example, a parallel-serial ADC might employ an interstage amplifier with a limiting operation. Assuming that a binary N bit analog-to-digital (A/D) conversion is performed by a typical two stage parallel-serial ADC, an input analog signal is applied to a first N/2 bit parallel ADC whose output is applied to a digital-to-analog converter (DAC) for reconstructing the input analog signal first quantized. The input signal may also be delayed by an amount equal to the delay due to the first N/2 bit parallel ADC and the DAC, and the reconstructed input signal is subtracted from the input signal by the interstage amplifier to produce an analog signal which is applied to the input of a second N/2 bit parallel ADC for providing an additional output digital signal which is combined with the output signal of the first N/2 bit ADC. It is desirable for the interstage amplifier to be a limiter circuit having differential inputs. Further, since such limiter circuit is used for A/D conversion, it is required to have high linearity and fast recovery.
FIG. 1 shows a prior art limiter circuit with differential inputs. This limiter circuit includes transistors 14 and 16 having their emitters coupled through resistors 18 and 20 having equal resistance values. An input voltage V.sub.in is applied between the bases of the transistors 14 and 16 through input terminals 10 and 12. Depending on use, the base of the transistor 16 may be grounded. A current source 22 is connected to the node of resistors 18 and 20 to flow common current 2I. Two current sources 24 and 26 each provide a current I to the collectors of the transistors from a positive voltage source +E. The output limit current is determined by the current I of the current sources 24, 26 and is derived from output terminals 28 and 30. The output current may be converted to voltage by a current-to-voltage converter, not shown.
When the input voltage V.sub.in is zero, the collector currents of the transistors 14 and 16 are both equal to I. When the input voltage V.sub.in increases, the collector current of the transistor 14 increases, while that of the transistor 16 decreases at the same rate. Assuming that the change in current is .DELTA.I, the collector currents of the transistors 14 and 16 are respectively I+.DELTA.I and I-.DELTA.I. Since each current source provides a constant current, the current difference .DELTA.I enters by way of the terminal 30 and leaves by way of the ouput terminal 28. When the input voltage V.sub.in increases still more, the current .DELTA.I is limited to the value I. Thus, the maximum output current is determined by current sources 24 and 26 and is equal to I.
The collector current Ic, generally, is represented as follows: EQU Ic=Is exp (qV/KT)
herein
q: charge of electron PA1 T: absolute temperature PA1 K: Boltzman Constant PA1 Is: saturation current PA1 V: voltage between the base and the emitter
According to the above equation, Ic versus V curve is very nonlinear. Therefore, it will be understood that the output current has an S-shaped characteristic between the two limited levels as shown by a solid line in FIG. 2. Such a non-linear characteristic is undesirable for the input stage limit circuit of an ADC. However, this limiter circuit has a very fast recovery from an overload condition, i.e. a limited condition. In this respect, the FIG. 1 limiter circuit is suitable for an ADC.